? semiconductor components industries, llc, 2012 march, 2012 ? rev. 1 1 publication order number: nop04811/d nop04811 400/300/200/100 dpi high-speed photodiode array description the nop04811 photodiode array (pda) provides selectable 400, 300, 200 and 100 dot per inch (dpi) resolution. the sensor contains an on ? chip output amplifier , internal power ? down capability and parallel transfer features that are uniquely combined with advanced active ? pixel ? sensor technology. applications for the photodiode sensor array include currency verification, bar code scanning and industrial process automation equipment. features ? 400, 300, 200 and 100 dpi selectable resolutions ? 232, 174, 116 or 58 image sensor elements (pixels) ? 63.45 m (400 dpi) pixel center ? to ? center spacing ? on ? chip amplifier ? single 3.3 v power supply ? 3.3 v input clocks and control signals ? 8.0 mhz maximum pixel rate ? parallel integration and transfer operations ? automatic power ? down of internal circuitry ? high sensitivity ? low power ? low noise ? this is a pb ? free device applications ? currency verification ? document scanning ? barcode scanning ? process automation equipment amp v out vref gbst so clk si vdd vss 0.1 f 10 f 50 k + 100 figure 1. typical application circuit 100 100 100 100 0.1 f photodiode array storage, transfer and readout registers micro controller gpio nop04811 rs1 rs2 olcc12 cl suffix case 755aa marking diagram http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. ordering information xxxxxxxx = specific device code a = assembly location y = year w = work week xxxxxxxx ayw (bottom view of package)
nop04811 http://onsemi.com 2 figure 2. pinout configuration 1 2 3 4 5 6 12 11 10 9 8 7 (top view) vout vss vref rs1 rs2 so test (nc) si gbst clk vdd nc table 1. pin function description pin pin name description 1 vout analog video output signal 2 vss ground 3 vref input reference voltage for the differential amplifier driving vout, sets the output reset (dark) voltage level 4 rs1 selects the 400, 300, 200 or 100 dpi resolution mode 5 rs2 (nc) has no functionality, this pad should be left unconnected 6 so end ? of ? scan output pulse used to drive the start pulse (si) input of the next sensor chip in a module 7 nc no connect, this pad should be left unconnected 8 vdd +3.3 v power supply 9 clk clock input for the shift register 10 gbst global start pulse initializes the start inputs of all sensor chips in a module and starts the scanning process of the first sensor chip 11 si start pulse, input to start a line scan 12 test (nc) test pad used during wafer sort, this pad should be left unconnected 1 2 3 230 231 232 229 row of 232 pixels (400dpi) and video line multiplexers test (nc) si gbst clk vdd vout vss vref rs1 rs2 (nc) so amplifier, power down, offset control parallel transfer, storage cells, readout registers scan direction left to right figure 3. simplified block diagram
nop04811 http://onsemi.com 3 table 2. absolute maximum ratings parameter symbol value unit power supply voltage v dd 4 v input voltage range for clk, si, gbst, rs1, vref v in v ss ? 0.5 to v dd +0.5 v storage temperature t stg ? 25 to 75 c storage humidity, non ? condensing h stg 10 to 90 % esd capability, human body model (note 1) esd hbm 2500 v esd capability, machine model (note 1) esd mm 250 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device incorporates esd protection and is tested by the following methods: esd human body model tested per eia/jesd22 ? a114 esd machine model tested per eia/jesd22 ? a115 latchup current maximum rating: 100 ma per jedec standard: jesd78 table 3. recommended operating ranges (unless otherwise specified, these specifications apply t a = 25 c) parameter symbol min typ max unit power supply voltage v dd 3.1 3.3 3.5 v power supply current, initialization ? first 100 clock cycles i dd_init 5.8 ma power supply current, integration and transfer mode i dd_oper 40 ma power supply current, idle mode, still integrating i dd_idle 3.2 ma low level input voltage for clk, si, gbst, rs1 v il v ss ? 0.5 0.6 v high level input voltage for clk, si, gbst, rs1 v ih 2.8 v dd + 0.1 v reference voltage v ref 1.1 1.2 1.3 v clock frequency f 0.5 8.0 8.0 mhz pixel rate (note 2) p r 0.5 8.0 8.0 mhz integration time (line scan rate) (note 3) t int 99.5 s resistive load on vout r l 50 50 k capacitive load on vout c l 150 pf operating temperature t op ? 10 50 c operating humidity, non ? condensing h op 10 85 % 2. one pixel is clocked out for every clock cycle. 3. tint is the integration time of a single sensor and is the time between two start pulses. the minimum integration time is the time it takes to clock out 100 inactive pixels and 232 active pixels for the 400 dpi mode, 100 inactive pixels and 174 active pixels for the 300 dpi mode, 100 inactive pixels and 1 16 active pixels for the 200 dpi mode or 100 inactive pixels and 58 active pixels for the 100 dpi mode, at a given frequency. table 4. physical specifications parameter symbol typ unit number of pixels, 400 dpi p n_400 232 number of pixels, 300 dpi p n_300 174 number of pixels, 200 dpi p n_200 116 number of pixels, 100 dpi p n_100 58 pixel ? to ? pixel spacing, 400 dpi d pp_400 63.45 m pixel ? to ? pixel spacing, 300 dpi d pp_300 84.60 m pixel ? to ? pixel spacing, 200 dpi d pp_200 126.90 m pixel ? to ? pixel spacing, 100 dpi d pp_100 253.80 m
nop04811 http://onsemi.com 4 table 5. switching characteristics (unless otherwise specified, these specifications apply t a = 25 c) (note 4) parameter symbol min typ max unit clk clock period (note 5) t o 125 2000 ns clk pulse width (note 5) t w 62.5 ns clk duty cycle (note 6) dc clk 45 50 55 % gbst setup time (notes 5, 7) t su 20 ns gbst hold time (notes 5, 7) t h 25 ns clk rise time (notes 5, 8) t r_clk 62.5 ns clk fall time (notes 5, 8) t f_clk 62.5 ns gbst rise time (notes 5, 8) t r_gbst 62.5 ns gbst fall time (notes 5, 8) t f_gbst 62.5 ns pixel output timing, clk = 8 mhz ts 75 ns pixel output rise time (note 9) p rt tbd ns 4. refer to figure 4 through figure 6 for more information on ac characteristics 5. assuming a 50% duty cycle. 6. defined as the ratio of the positive duration of the clock to its period. 7. the shift register loads on the falling edge of clk, therefore setup and hold times (tsu, th) are needed to prevent loading o f multiple start pulses. this would occur if gbst remains high during two fallings edges of the clk signal. see figure 4. 8. clock rise time should match clock fall time. 9. pixel output rise time measured at 8 mhz with 150 pf and 50 k load to ground with the output at saturation. table 6. electro ? optical characteristics test conditions parameter symbol value unit power supply voltage v dd 3.3 v reference voltage v ref 1.2 v clock frequency f 8.0 mhz clock pulse duty cycle dc cp 50 % integration time, 400 dpi t int_400 41.5 s integration time, 300 dpi t int_300 34.25 s integration time, 200 dpi t int_200 27.0 s integration time, 100 dpi t int_100 19.75 s resistive load on vout (note 10) r l 50 k capacitive load on vout (note 11) c l 150 pf average output voltage swing (note 12) v avg 1.0 v led peak wavelength (note 13) p 550 nm operating temperature t op 25 c 10. resistive load connected between vout and vref. vref is typically has a lower noise level than vss. 11. capacitive load connected between vout and vss. 12. the average output voltage vavg is defined as the voltage difference between the average pixel level in the light and the av erage pixel level in the dark. it should be adjusted to approximately 1.0 v, unless stated otherwise. 13. a linear array of uniform green leds acts as the light source for measurements requiring illumination, unless otherwise stat ed.
nop04811 http://onsemi.com 5 table 7. electro ? optical characteristics (unless otherwise specified, these specifications were achieved with the test conditions defined in table 6) parameter symbol min typ max unit dark output voltage (note 14) v d v ref ? 0.150 v ref v ref + 0.150 v dark output non ? uniformity (note 15) u d 0 100 mv photo ? response non ? uniformity (note 16) u p ? 15 15 % adjacent pixel photo ? response non ? uniformity (note 17) u padj 0 15 % saturation voltage (note 18) v sat 1.2 v sensitivity, 400 dpi (note 19) s v_400 2135 v/ j/cm 2 sensitivity, 300 dpi (note 19) s v_300 tbd v/ j/cm 2 sensitivity, 200 dpi (note 19) s v_200 tbd v/ j/cm 2 sensitivity, 100 dpi (note 19) s v_100 tbd v/ j/cm 2 photo ? response linearity (note 20) prl 99 107 % individual rms pixel noise, 400 dpi (note 21) p _noise 0 3 15 mv image lag (chip average) (note 22) il 1 % 14. vd is the average dark output level and represents the offset level of the video output in the dark. the dark level is set b y vref and is recommended to be 1.2 v for optimal module operation. 15. ud = vdmax ? vdmin, where vdmax is the maximum pixel output voltage in the dark vdmin is the minimum pixel output voltage in the dark in the 400 dpi mode, dark output non ? uniformity is tested at 4 ms. 16. up = [(vpmax ? vpavg)/vpavg] x 100%, or [vpavg ? vpmin)/vpavg] x 100%, whichever is greater, where vpmax is the maximum pixel voltage of any pixel at full bright vpmin is the minimum pixel voltage of any pixel at full bright vpavg is average output voltage of all pixels at full bright. 17. upadj = max [ | (vp(n) ? vp(n+1) | / vpavg] x 100%, where upadj is the nonuniformity in percent between adjacent pixels for a bright background vp(n) is the pixel output voltage of pixel n at full bright. 18. vsat is defined as the maximum video output voltage swing measured from the dark level to the saturation level. it is measur ed by using the module led light source with the module imaging a uniform white target. the led light level is increased until the output v oltage no longer increases with an increase in the led brightness. 19. sv is defined as the slope of the vpavg vs. exposure curve. sensitivity uniformity is nominally better than 10% die ? to ? die. 20. prl = ((vratio ? tratio) / tratio) x 100%, where vratio = (vavg3 ? vavg1) / (vavg2 ? vavg1) tratio = (tint3 ? tint1) / (tint2 ? tint1) tint1 is the integration time needed to get a vavg1 of about 0.1 v tint2 is the integration time needed to get a vavg2 of about 0.5 v tint3 is the integration time needed to get a vavg3 of about 0.9 v a specification limit of 5% for this test method is a tighter spec than 5% deviation from a best fit line. linearity is specified within the range of the saturation voltage. 21. individual rms pixel noise is defined as the standard deviation of each pixel in the dark. this can also be considered outpu t referred noise as it is measured at the sensor output. 22. image lag is defined as taking two subsequent cis reads where the first readout occurs when the sensor is illuminated such that the i mager output voltage is in saturation and the second readout occurs with zero irradiance falling on the sensor.
nop04811 http://onsemi.com 6 2 3 98 99 100 101 102 103 307 308 309 310 329 330 331 332 400dpi clk # 2 3 98 99 100 101 102 103 249 250 251 252 271 272 273 274 300dpiclk # 2 3 98 99 100 101 102 103 191 192 193 194 213 214 215 216 200dpiclk # 2 3 98 99 100 101 102 103 133 134 135 136 155 156 157 158 100dpiclk # 1 2 207 208 209 210 229 230 231 232 400dpi pixel # 149 150 151 152 171 172 173 174 300dpipixel # 91 92 93 94 113 114 115 116 200dpipixel # 33 34 35 36 55 56 57 58 100dpipixel # 12 12 12 400dpi 300dpi 200dpi 100dpi 100 inactive pixels (100 clocks) 100 inactive pixels (100 clocks) 100 inactive pixels (100 clocks) 100 inactive pixels (100 clocks) 232active pixels(232clocks) 174active pixels(174clocks) 116active pixels ( 116clocks) 58activepixels (58 clocks) gbst clk so vout number of pixels (clocks) per readout section 3 3 3 3 11 0110 1011 1 1 1 1 1 figure 4. overall timing diagram for 400/300/200/100dpi modes 50% 50% 50% gbst clk so vout ts 80% 10% 90% 10% 90% figure 5. rise and fall times for 400/300/200/100dpi modes p rt t f_so t r_so t r_clk t f_clk v ss v ref v sat t h t f_gbst t r_gbst t su t o t w t w
nop04811 http://onsemi.com 7 1 2 3 99 101 102 103 123 gbst clk vout figure 6. timing of gbst ? to ? first pixel for 400/300/200/100 dpi modes t su t su t h t h 305 306 307 308 309 310 330 331 332 400d p i clk # 247 248 249 250 251 252 272 273 274 300d p i clk # 189 190 191 192 193 194 214 215 216 200d p i clk # 131 132 133 134 135 136 156 157 158 100d p i clk # 207 208 209 210 230 231 232 400d p i p i xel # 149 150 151 162 172 173 174 300d p i p i xel # 91 92 93 94 114 115 116 200d p i p i xel # 33 34 35 36 56 57 58 100d p i p i xel # clk so v out 205 206 147 148 89 90 31 32 figure 7. timing of si/so clock for 400/300/200/100 dpi modes
nop04811 http://onsemi.com 8 description of operation functional description the nop04811 photodiode array has selectable 400, 300, 200 and 100 dpi resolution. the sensor contains an on ? chip output amplifier, automatic power ? down circuitry and parallel transfer features that are uniquely combined with advanced active ? pixel ? sensor technology. the image photodiode array is designed to be part of an image acquisition system including the necessary optical lens as illustrated figure 1. figure 3 is a block diagram of the sensor. each sensor consists of 232 active pixels, their associated multiplexing switches, buf fers and an output amplifier circuit with power down. the pixel ? to ? pixel spacing is 63.45 m. there are a number of features incorporated into the nop04811 which improve the sensor?s performance. active pixel technology active pixel technology supplements the primary photodiode sensor element with additional transistors which condition, amplify and buffer the original signal. figure 8 illustrates a pair of active pixel cells connected to the internal scan line. sel reset vdd sel reset vdd figure 8. active pixel cell architecture pixel ? to ? pixel offset cancellation circuit the sensor employs a pixel ? to ? pixel offset cancellation circuit, which reduces the fixed pattern noise (fpn) and amplifier offsets. this innovative circuit design greatly improves the optical linearity and low noise sensitivity. parallel integrate, hold and transfer the sensor has a parallel integrate, transfer and hold feature which allows the sensor to scan data out while photon integration is taking place. these features are approached through the use of an integrate ? and ? hold cell located at each pixel site. each pixel?s charge is read from its storage site as the shift register sequentially selects each pixel and transfers each pixel?s charge onto a common video line. scan initiation inputs gbst and si the sensor has two scan initiation inputs, the global start pulse (gbst) and the start pulse (si) which are compatible with standard 3.3 v cmos signal levels. the scan cycle starts when gbst is captured on the falling edge of the clock input (clk). during the first 100 clock cycles following a gbst pulse, all the pixels cycle through their pre ? scan initialization process that reduces fpn and reset noise. si selects when an individual sensor is selected. by permanently asserting the si pin, the scanning sequence is properly initialized. the sensor clocks out 100 inactive pixels before accessing its first active pixel. during these 100 clock cycles, the sensor cycles through the pre ? scan initialization process. after initialization, the sensor starts its read cycle with its first ? active pixel appearing on the 100th clock cycle. power saving mode the sensor incorporates an internal power ? saving feature. when the si pin of a particular sensor is selected for read out, the sensor powers up the output amplifier and then powers it down when the read scan is completed. common reference voltage the sensor has an input bias control (vref), which serves as an offset voltage reference for the output amplifier. in multiple chip operation, the vref inputs are tied together such that each sensor references the same bias level. selectable resolutions of 400, 300, 200 and 100 dpi the select resolution input (rs1) is used to select between 400, 300, 200 and 100 dpi modes. ? for 400 dpi, the rs1 input is held high (vdd) ? for 300 dpi, the rs1 input is held low (vss) ? for 200 dpi, the rs1 input is held low for clocks 20, 21 and 22 and then high for clocks 44, 45 and 46 ? for 100 dpi, the rs1 input is held high for clocks 20, 21 and 22 and then low for clocks 44, 45 and 46 in 400 dpi mode, all 232 pixels are clocked out. in the 300 dpi mode, pixels 1 and 1/2 of pixel 2 are combined, 1/2 of pixel 2 and 3 are combined. pixel 4 and 1/2 of pixel 5 are combined and 1/2 of pixel 5 and pixel 6 are combined and so on up to 1/2 of pixels 231 and 232 being combined. this will give a net pixel count of 232 pixels. similarly, in 200 dpi mode, pixels 1 and 2 are combined and pixels 3 and 4 are combined and so on up to pixels 231 and 232 being combined. in 100 dpi mode, pixels 1, 2, 3 and 4 are combined, pixels 5, 6, 7 and 8 are combined and so on up to pixels 229, 230, 231 and 232 being combined.
nop04811 http://onsemi.com 9 in the 300 dpi mode, one quarter of the pixel amplifiers and one quarter of the scanning register are disabled when compared to the 400 dpi mode. as a result, sensitivity in the 300 dpi mode will be 1.5 times that of the 400 dpi mode. the 300 dpi readout time will be approximately three quarters of the 400 dpi readout time. similarly, in 200 dpi mode one half of the pixel amplifiers and one half of the scanning registers are then disabled. as a result, sensitivity in the 200 dpi mode will be twice that of the 400 dpi mode. the 200 dpi readout time will be approximately a half of the 400 dpi readout time. in the 100 dpi mode three quarters of the pixel amplifiers and three quarters of the scanning registers are disabled. sensitivity in 100 dpi mode is four times the sensitivity in 400 dpi mode. the 100 dpi readout time will be approximately one quarter of the 400 dpi readout time. unlike a ccd array, the 400 dpi, 300 dpi, 200 dpi and 100 dpi modes all operate at the same clock frequency. timing figure 4 shows the initialization of the sensor for the 400 dpi, 300 dpi, 200 dpi and 100 dpi modes. the sensor will operate with 100 inactive pixels being clocked out before its first active pixel is clocked out. figure 4 and figure 5 detail the timing of the clk, gbst, out, and si/so signals in further detail, they have the same timing requirements for the 400, 300, 200 and 100 dpi modes. the rise and fall times are listed in table 5. in figure 6, note that clock 100 is the first active pixel, as the first 100 clocks produce dummy pixels (the output of the first 100 clocks should not be used for any purpose such as black level clamping). figure 7 shows the timing of the so signal for the 400 dpi, 300 dpi, 200 dpi and 100 dpi modes, which corresponds with the 208th pixel for the 400 dpi mode, 150th pixel for the 300 dpi mode, the 92nd pixel for the 200 dpi mode and 34th pixel for 100 dpi mode. the sensor?s so signal can be used to determine when the end of the scan is reached. the last active pixel the sensor is the 232th pixel for the 400 dpi mode, 174th pixel for the 300 dpi mode, the 116th pixel for the 200 dpi mode and 58th pixel for the 100 dpi mode. 19 20 21 22 23 43 44 45 46 47 clk gbst 99 100 101 1 2 rs 1 ? 400dp i rs 1 ? 300dp i rs 1 ? 200dp i rs 1 ? 100dp i figure 9. resolution select input timing ordering information device package temperature range shipping ? NOP04811CLTAG olcc12 (pb ? free) ? 40 c to +85 c 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nop04811 http://onsemi.com 10 package dimensions olcc12 20x5, 3.0p case 755aa issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension a includes the package body and lid but does not include heatsinks or other attached features. 4. the glass lid defined by dimensions d2 and e2 must be located within dimensions d and e. 5. pin one indicator shall be as shown in this location. dim a min max millimeters 1.37 1.77 a2 0.50 ref b 0.75 0.85 d2 19.00 ref d 19.90 20.10 e2 4.00 ref 4.90 5.10 e e 3.00 bsc 1.15 1.25 l detail a note 5 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* recommended 0.10 0.20 l1 a1 1.00 ref 3.00 1.58 12x dimensions: millimeters 0.80 pitch 5.30 12x 1 package outline d e note 4 detail a glass lid top view b a seating plane a2 a a1 0.08 c note 3 side view c l e b 6 7 12x 1 12 12x bottom view note 4 d2 e2 l1 12x e/2 s b m 0.05 c s a on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 nop04811/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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